[Verilog] 再次征戰FIFO地獄 - (2) sync fifo

前面介紹完sync fifo的function block用途後,

這篇開始來帶入code要怎麼implement.

Full code:

module sync_fifo #(parameter N=8, parameter depth=8)
(input clk,
input rst_n,
input [N-1:0] wdata,
output [N-1:0] rdata,
input wen,
input ren,
output full,
output empty
);

// mem 
reg [N-1:0] mem [depth-1:0];
// ptr
reg [$clog2(depth)-1 :0] wptr,rptr;
//cnt
reg [$clog2(depth)-1 :0] cnt;

//------------- mem w/r --------------//
// mem write
always @ (posedge clk) begin
	if (wen & !full)
		mem [wptr] <= wdata;
end
//mem read
always @ (posedge clk or negedge rst_n) begin
	if (!rst_n)
		rdata <= 'b0;
	else if (ren & !empty)
		rdata <= mem [rptr];
end

//------------------ ptr --------------------//
// wptr
always @ (posedge clk or negedge rst_n) begin
	if (!rst_n)
		wptr <= 'b0;
	else if (wen & !full)
		wptr <= wptr + 'd1;
end	
// rptr
always @ (posedge clk or negedge rst_n) begin
	if (!rst_n)
		rptr <= 'b0;
	else if (ren & !empty)
		rptr <= rptr + 'd1;
end

//------------------- cnt --------------------//
//cnt
always @ (posedge clk or negedge rst_n) begin
	if (!rst_n)
		cnt <= 'd0;
	else if (wen & !full & !(ren & !empty))
		cnt <= cnt + 'd1;
	else if (ren & !empty & !(wen & !full))
		cnt <= cnt - 'd1;
end
	
//--------------- full/empty------------------//	
// full
assign full = (cnt == depth)? 1:0;
//empty
assign empty = (cnt == 'd0)? 1:0;

endmodule

要如何簡單的理解這個code的內容

我們可以利用每個function block的功能慢慢的組出

主要的block有4個部分

(1) mem : write data / read data